Modern high density dynamic memory structures (e.g., dynamic random access memory or DRAM) are based upon a single device plus capacitor storage concept described in U.S. Pat. No. 3,387,282. The first implementation of which used planar capacitors and transistors. An example of one structure using planar structures is shown in FIG. 1. The memory structures 10 individually include interlayer dielectric material 11, a bitline 12, a bitline contact 13, an n-well of a semiconductive substrate 14, p+ active areas 15, a wordline 16, gate polysilicon 17, and gate oxide 18. These structures led to dramatic increases in memory density and decreases in per bit cost. As the density of DRAM increases, the space available for capacitors is reduced.
The desire for devices of increased density and sufficient capacitance led to the development of new memory structures. Referring to FIGS. 2 and 3, examples of more recently developed devices are shown. FIG. 2 shows exemplary stacked capacitor memory structures 20 individually comprising interlayer dielectric material 21, a bitline 22, a bitline contact 23, a p-substrate 24, n+ active areas 25, a wordline 26, field polysilicon 27, field oxide 28, and cell plates 29.
FIG. 3 shows exemplary trench capacitor memory structures 30 individually comprising interlayer dielectric material 31, a bitline 32, a bitline contact 33, a p− substrate or well 34, n+ active areas 35, a wordline 36, field polysilicon 37, field oxide 38, a polysilicon strap 39, a polysilicon storage node 40, ONC dielectric 41, and a heavily doped substrate region 42. The structures of FIGS. 2 and 3 permitted the use of a vertical capacitor which led to continued increase in density for several generations of DRAM design.
The progress however was not without a cost. The minimum capacitance required for effective electrical operation does not scale with the reduction in achievable photolithographic dimensions (i.e., the size of the capacitor (area) remains relatively constant). To achieve this while reducing the total size of the cell resulted in either an increase in the vertical dimension of the capacitor while the horizontal dimensions were decreased and/or required the thickness of the dielectric to be decreased. Thus, trench capacitors having increasing depth became more difficult to build. Stacked capacitors grew taller and led to processes to roughen the surface (thereby increasing the capacitor area). These improvements including increasing the height of the capacitor structures led to difficulties in producing wiring layers above the capacitor structures along with very high aspect ratio contacts. Proposals have been made to use dielectrics other than Nitride-Oxide combinations typically used. However, these proposals have proved difficult to impossible to implement. There is a desire to increase the space available for construction of the capacitor while at the same time reducing the total cell area.